🚀 Senior Architect: Compute and Dataflow

About Etched

Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real‑time video generation models and extremely deep & parallel chain‑of‑thought reasoning agents. Backed by hundreds of millions from top‑tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

We are seeking a highly motivated and skilled Research Scientist with deep expertise in chip microarchitecture , dataflow‑centric design , and interconnect/network‑on‑chip (NoC) optimization to join our central architecture team. This role focuses on pushing the boundaries of performance, efficiency, and scalability for next‑generation compute systems by exploring novel microarchitectural innovations and optimizing data movement across the compute fabric.

You will work on cutting‑edge problems in defining the architecture of our core compute engines, optimizing them for best PPA, and collaborating with cross‑disciplinary teams to prototype and evaluate new ideas and concepts, and eventually make it to a state‑of‑the‑art chip and system we are building.

Key responsibilities

• Drive research and development of next‑generation chip microarchitecture with a focus on dataflow‑centric and interconnect/NoC optimization.
• Prototype and evaluate end‑to‑end compute systems.
• Build performance and power models for our next generation chips.
• Collaborate with cross‑disciplinary teams to explore architectural innovations that enhance performance, efficiency, and scalability.
• Contribute to shaping future computing platforms in AI/ML and cloud infrastructure.

You may be a good fit if you have

• A PhD in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field, or equivalent practical experience.
• Experience in microarchitecture design and hardware‑software co‑design.
• Proficiency in systems‑level programming languages such as C or C++.
• A strong research background in computer systems design and architecture.
• Expertise in chip microarchitecture, dataflow architectures, and network‑on‑chip/interconnect systems.
• Experience with memory hierarchy design, interconnect topologies, coherence protocols, and scalable compute fabrics.

Strong candidates may also have experience with

• Publishing in top‑tier venues such as ISCA, MICRO, ASPLOS, HPCA, DAC, and SIGARCH.
• Hardware modeling tools such as gem5, RTL simulation, or cycle‑accurate simulators, along with performance analysis methodologies.
• Systems for machine learning (ML), accelerators, and heterogeneous compute platforms.
• Designing and building experimental or production‑grade computing systems.

Benefits

• Full medical, dental, and vision packages, with generous premium coverage
• Housing subsidy of $2,000/month for those living within walking distance of the office
• Daily lunch and dinner in our office
• Relocation support for those moving to West San Jose

Compensation Range

• $150,000 - $275,000

How we’re different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model‑specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single‑model ASICs.

We are a fully in‑person team in West San Jose, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

#J-18808-Ljbffr