π Sr. FPGA Engineer
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Cytek Biosciences
- π Location: Seattle
- π Posted: Oct 28, 2025
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This range is provided by Cytek Biosciences. Your actual pay will be based on your skills and experience β talk with your recruiter to learn more.
Base pay range
$150,000.00/yr - $200,000.00/yr
Summary
Develop, integrate, maintain, and support Verilog/VHDL FPGA pipeline implementations on the full line of Cytek flow cytometers. The primary focus is applications for instrument control, real-time signal and image processing, high throughput data acquisition, statistical analysis, and optimization of data throughput.
Essential Duties And Responsibilities
- Design, develop, and verify complex digital systems using Verilog HDL for implementation on FPGA platforms.
- Perform detailed timing analysis, resource optimization, and power estimation for FPGA designs.
- Implement and debug complex digital signal processing algorithms and control systems on FPGAs.
- Perform board bring-up and system-level testing of FPGA-based designs.
- Collaborate with electronics engineers to integrate analog and digital components into FPGA-based systems.
- Design and implement interfaces between FPGAs and analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and other analog devices.
- Create FPGA verification and test plans according to system specifications.
The requirements listed below are representative of the knowledge, skill, and/or ability required.
- Bachelors/Master's degree in Electrical Engineering/Computer Science/Information Systems is highly desirable or Master's/Ph.D. degree a related field.
- Understanding of digital design principles, including timing analysis, state machine design, and pipelining.
- Experience in developing new components and supporting, modifying, and maintaining systems and code developed by others.
- Experience with microprocessors and CUDA software development is a plus.
- Experience implementing high-speed interfaces is a plus (e.g., PCIe, Ethernet, SFP+).
The physical demands described here are representative of those that an employee must meet to perform the essential functions of this job successfully. Reasonable accommodations may be made to enable individuals with disabilities to perform essential functions.
Seniority level
Seniority level
Mid-Senior level
Employment type
Employment type
Full-time
Job function
Job function
Engineering and Information Technology
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